36 Parti: Essentials
location, you need to specify a 16-bit segment selector and a 32-bit offset within
the segment. The segmentation scheme is more advanced than that in 8086. The
8086 segments start at a fixed location and are always 64K in size. With 80386, you
can specify the starting location and the segment size separately for each segment.
Segments may overlap - that is, two segments can share address space. The nec-
essary information (the starting offset, size, and so forth) is conveyed to the proces-
sor via segment tables. A segment selector is an index into the segment table. At
any time, only two segment tables can be active: a Global Descriptor Table (GOT)
and a Local Descriptor Table (GOT). A bit in the selector indicates whether the
processor should refer to the LOT or the GDT. Two special registers, GDTR and
LDTR, point to the GDT and the LOT, respectively. The instructions to load these
registers are privileged, which means that only the operating system code can exe-
cute them.
A segment table is an array of segment descriptors. A segment descriptor speci-
fies the starting address and the size of the segment. You can also specify some ac-
cess permission bits with a segment descriptor. These bits specify whether a
particular segment is read-only, read-write, executable, and so on. Each segment
descriptor has 2 bits specifying its privilege level, called as the descriptor privilege
level (DPL).
The processor compares the DPL with the Requested Privilege Level (RPL) before
granting access to a segment. The RPL is dictated by 2 bits in the segment selector
while specifying the address. The Current Privilege Level (CPL) also plays an impor-
tant role here. The CPL is the DPL of the code selector being executed. The proces-
sor grants access to a particular segment only if the DPL of the segment is less than
or equal to the RPL as well as the CPL. This serves as a protection mechanism for
the operating system. The CPL of the processor can vary between 0 and 3 (because
2 bits are assigned for CPL). The operating system code generally runs at CPL=0,
also called as ring 0, while the user processes run at ring 3. In addition, all the seg-
ments belonging to the operating system are allotted DPL=0. This arrangement en-
sures that the user mode cannot access the operating system memory segments.
It is very damaging to performance to consult the segment tables, which are
stored in main memory, for every memory access. Caching the segment descriptor
in special CPU registers, namely, CS (Code Selector), DS (Data Selector), SS (Stack
Selector), and two general-purpose selectors called ES and FS, solves this problem.
The first three selector registers in this list- that is, CS, DS, and SS - act as default
registers for code access, data access, and stack access, respectively.
To access a memory location, you specify the segment and offset within that
segment. The first step in address translation is to add the base address of the seg-
ment to the offset. This 32-bit address is the physical memory address if paging is
not enabled. Otherwise this address is called as the logical or linear address and is
converted to a physical RAM address using the page address translation mechanism
(refer to Figure 4-1).
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